Micro-Ring Silicon Optical engine · Enabling High-Speed Optical Interconnects for AI Computing Clusters
Lingxi Photonics’ CPO microring optical engine leverages advanced Microring Modulator (MRM) technology to co-package optical I/O with switching and accelerator silicon, enabling high-bandwidth-density, energy-efficient optical interconnects for next-generation AI infrastructure.
With a device footprint of approximately one-hundredth that of a conventional Mach–Zehnder Modulator (MZM), microring technology enables significantly higher integration density and lower power consumption, making it a key building block in the transition from electrical to optical connectivity in AI data centers.
Interconnect: Switches, Network Interface Cards
Scenarios: Between racks, computing clusters
Protocols: InfiniBand, UEC
Requirements: Maintainability, flexible networking
In scale-out architectures, conventional pluggable optical modules rely on DSPs to compensate for signal degradation over long electrical paths, with power consumption reaching 20–30 W per module. At the same time, front-panel I/O density is approaching its practical physical limits.
Lingxi Photonics’ CPO microring optical engine brings optical I/O closer to the switching and accelerator silicon, shortening electrical signal paths from centimeters to millimeters and reducing link loss from approximately 20 dB to just 4 dB. This enables high-quality signal transmission without DSP-based compensation, while simultaneously reducing link power consumption and latency.
At comparable system configurations, overall system power can be reduced by approximately 40%, with energy efficiency reaching the 5 pJ/bit range. The result is higher port density and greater switching capacity within the same rack footprint, providing a more scalable interconnect architecture for next-generation AI infrastructure.
Interconnect: Switch, XPU
Scenarios: Rack, Supernode
Protocols: NVLink, UALink, Huawei UB
Requirements: Bandwidth Density, Power Consumption, Latency
In scale-up architectures, in-rack copper interconnects are limited to effective transmission distances of only 1–3 meters at 200G per lane. As accelerator integration density and interconnect bandwidth requirements continue to rise, copper-based connectivity is approaching its fundamental limits.
Lingxi Photonics’ microring optical engine is positioned close to the accelerator package and supports 16 or 32 high-speed signal lanes, replacing long-reach copper links with optical interconnects. This overcomes the dual constraints of distance and interconnect density inherent to copper, while enabling shoreline bandwidth density on the order of 1 Tbps/mm with significantly lower power consumption. The result is a high-density, energy-efficient optical interconnect architecture designed to support thousand-accelerator-class supernodes and the rapidly growing bandwidth demands of next-generation AI systems.
Interconnect: XPU、HBM
Scenarios: Internal Interconnects in Single-Board Card Packages
Protocols: UCIe、PCIe
Requirements: Channel Density, Ultra-Low Power Consumption, and Ultra-Low Latency
For in-package interconnects, electrical interfaces such as UCIe and PCIe are approaching fundamental limits in both shoreline bandwidth density and energy efficiency. With a footprint of only about one-hundredth that of a conventional Mach–Zehnder Modulator (MZM), microring modulators also support dense wavelength-division multiplexing (DWDM), enabling optical I/O to be integrated directly into the chip package.
This architecture delivers energy efficiency in the fJ/bit range and shoreline bandwidth density on the order of 1 Tbps/mm, overcoming the scaling constraints of electrical interconnects and providing a scalable optical I/O interface for next-generation XPUs.
Lingxi Photonix