Careers

■ CPO Optical Engine RDL Interconnect Design: Responsible for the high-density interconnect design of CPO (Co-Packaged Optics) optical engine modules, including RDL (redistribution layer) layout design on interposers / interconnect bridges, microbump array planning, TSV/TMV layout, and high-speed signal routing optimization between the optical engine and electrical chips (ASIC/Switch).

■ SI/PI High-Frequency Simulation & Optimization: For high-speed signal links at single-lane 100 Gbps and above (PAM4/NRZ), conduct signal integrity (SI) and power integrity (PI) simulation, including impedance control, insertion loss / return loss (IL/RL), crosstalk analysis, eye-diagram evaluation, IR drop analysis, and decoupling capacitor placement optimization. Use tools such as Ansys HFSS/SIwave, Cadence Sigrity, and Keysight ADS.

■ High-Speed Substrate & Packaging Co-Design: Participate in the high-speed substrate (Substrate/FCBGA) design of the CPO optical engine, and collaborate with substrate vendors to define stack-up structure, trace width/spacing rules, impedance targets, and DRC rules. Optimize BGA breakout, RDL fan-out, and the high-speed channel between the optical engine and the main board.

■ Electrical-Thermal-Mechanical Multi-Physics Simulation: Perform package-level thermal simulation (steady-state/transient) to evaluate the thermal distribution and temperature rise of the optical engine under high-speed operating conditions. Combined with warpage simulation and thermo-mechanical stress analysis, optimize RDL structure, material selection, and packaging process parameters to ensure yield and reliability.

■ Sample Testing & Verification Loop: Support the electrical testing of package samples (TDR/TDT, S-parameters, eye diagram, IR drop measurement), compare simulation with test results, and iteratively optimize the design. Conduct root cause analysis (RCA) on SI/PI/thermal/warpage issues and develop design guidelines.

■ Cross-Team Collaboration: Work closely with the silicon photonics chip design, optical packaging, ASIC design, system architecture, test & verification, and supply chain teams to drive end-to-end R&D and mass-production rollout of CPO optical interconnect products.

Job Requirements

Required Qualifications

• Proficient in package-level SI/PI simulation tools (Ansys SIwave/HFSS, Cadence Sigrity, Keysight ADS, etc.), with modeling and simulation experience in RDL, bump, TSV, interposer, and related structures

• Understanding of advanced packaging processes (WLP, 2.5D/3D integration, heterogeneous integration), with RDL design or substrate design experience

• Knowledge of high-speed signal link design (≥112 Gbps NRZ/PAM4), with understanding of S-parameters, eye diagram, COM, and other metrics

• Master's degree or above in Microelectronics / Electronic Packaging / Integrated Circuits / Electrical Engineering / Materials Science or related fields

Preferred Qualifications

• Experience in high-speed link design and simulation at single-lane 100 Gbps and above (e.g., 112 Gbps / 224 Gbps PAM4)

• Experience in high-speed substrate (FCBGA, high-layer-count PCB) design, familiar with substrate stack-up and impedance control

• Hands-on project experience in CPO / OIO / AI Accelerator optoelectronic co-packaging

• Thermal simulation capability (Ansys Icepak / Flotherm / COMSOL), able to perform steady-state/transient thermal analysis

• Structural stress and warpage simulation capability (Ansys Mechanical / Abaqus), with analysis experience in package thermo-mechanical reliability

• Familiarity with RDL process PDK usage, or collaboration experience with Foundry / OSAT

Bonus Points

• Candidates with full-flow simulation capability across SI + PI + Thermal + Stress are preferred

• Mass-production experience with CPO optical engine products

• Reliability simulation experience (EM / electromigration, TDDB, etc.)

• Python / MATLAB automation scripting capability

What We Offer

• Competitive compensation and benefits: five social insurances and housing fund, paid annual leave, and rental subsidy

• Cutting-edge CPO optical interconnect and advanced packaging R&D opportunities, with direct involvement in defining next-generation data center optical interconnect products

• Deep collaboration with silicon photonics, packaging, and system full-stack teams, and a complete technical growth path

• Flexible work arrangements and an open technical culture